Analog Devices EE-167 Introduction to TigerSHARC Multiprocessor Systems Using VisualDSP++

This document is a technical note on using Analog Devices' DSP components and development tools. It provides an introduction to TigerSHARC® multiprocessor systems using VisualDSP++™.


Analog Devices EE-167 Introduction to TigerSHARC Multiprocessor Systems Using VisualDSP++ - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Application Note
Language
English
Pages
12
File format
PDF
File size
579 KB
Published
03 August, 2012
Updated
29 September, 2023
MD5 checksum
6DC7F2C623A8E3366B3C6E9B4CC036AB

About this manual

This document serves as an introduction to multiprocessor (MP) system implementation using Analog Devices TigerSHARC processors and the VisualDSP++ 3.0 development environment. It focuses on systems where processors share the external bus, utilizing assembly code examples written for the ADDS-TS101S EZ-Kit Lite, which consists of two TigerSHARC processors.

The guide details the configuration of Linker Description Files (LDF) for multiprocessor projects, explaining commands such as MPMEMORY, MEMORY, PROCESSOR, and SHARED_MEMORY. It further covers the Multiprocessor Memory Space (MMS), external memory setup (specifically SDRAM), Vector Interrupts (VIRPT) for inter-processor communication, and the use of semaphores for task synchronization.

What's inside

  • Introduction
  • Linker Description File (LDF)
  • Multiprocessor Memory Space (MMS)
  • External Memory
  • Vector Interrupt (VIRPT)
  • Bus Lock and Semaphores

Frequently asked questions

What hardware kit is used for the assembly code examples in this note?

The examples are based on the ADDS-TS101S EZ-Kit Lite, which consists of two TigerSHARC processors.

What is the maximum number of ADSP-TS101S processors supported in one LDF?

The maximum number of processors that can be declared in one LDF is eight.

Which DSP ID is required to initialize SDRAM in a multiprocessor system?

A DSP with ID=000 must be present because it performs the initialization of the SDRAM.

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