Describes how to use the Analog Devices ADSP-21xx family of Digital Signal Processors to control the ADV601 video codec chip's video compression
This document explains how to use an Analog Devices ADSP-21xx family Digital Signal Processor (DSP) to control video compression in the ADV601 Video Codec chip. It details the design of the DSP to ADV601 interface and provides software for programming the DSP to manage the 'Bin Width Calculator' function.
The text describes the operation of the Bin Width Calculator, which adjusts 42 bin width and reciprocal bin width registers to achieve a desired compression ratio. It compares DSP-based versus host-based implementations, highlighting advantages such as real-time computation within the 1.2 milliseconds vertical retrace time and easier program development.
| Vertical retrace time for bin width computation | 1.2 milliseconds |
|---|---|
| Number of sub-bands | 42 |
| Processor family | ADSP-21xx |
Its duty is to set all 42 bin width and 42 reciprocal bin width registers with the proper fraction to achieve the desired compression ratio.
It responds to video changes by altering the bin-width register settings to achieve the desired bit rate, ensuring a constant bit rate for fixed communication links.
The DSP can compute new bin widths within the 1.2 milliseconds vertical retrace time, which is difficult to achieve in a host because Windows is not a real-time operating system.