This document provides some notes on using Analog Devices' DSP, audio, and video components. It presents benchmarks for Link Port throughput on the ADSP-2106x floating point family DSPs and discusses a design that uses 3 link ports for transmitting and receiving while other IOP activity is happening at the same time.
The document provides benchmark calculations for the maximum throughput achievable through all six link ports on the ADSP-2106x DSPs under various clock speeds (40MHz and 80MHz) and word sizes (32-bit and 48-bit). It explains that sustained performance depends heavily on whether 32-bit or 48-bit words are used, with 48-bit transfers allowing all six ports to operate simultaneously at higher clock rates. The text details the timing progression of data transfers per cycle to illustrate why certain configurations limit the number of active link ports.
| Maximum sustained throughput (40MHz, 32/48 bit words) | > 120Mbytes/sec |
|---|---|
| Maximum sustained throughput (80MHz, 48-bit words) | > 240Mbytes/sec |
| Sustained throughput with 32-bit words at 80MHz (4 ports active) | > 160Mbytes/sec |
| Max IOP bus bandwidth with on-chip RAM | 1 word/cycle |
| Link port overhead for DMA chaining restart | 8 cycles |
The word size is the limiting factor; 4 transfers are needed to transmit a full 32-bit word, causing delays where some ports wait for IOD service.
Yes, because 6 transfers are needed to transmit the entire 48-bit word, allowing continuous operation for all ports.
The IOP bus becomes the bottleneck, limiting the rate to approximately 39.7 Mwords/s when DMA chaining is used.
Yes, link Buffer 3 can only be used to transmit and not receive on these specific parts.