This document describes the link port booting process, including the perspective of the master device and the slave SHARC.
This Engineer's Note discusses the link boot process from both the perspective of the master device and the slave SHARC processor. It details how the link control register (LCTL) is handled during booting mode, noting that it is initialized to zero but ignored initially.
The document provides a step-by-step example of link port booting, including documented code for a master SHARC transferring boot code to a slave SHARC through link ports. It also covers the general SHARC booting process and specific hardware issues associated with link port booting.
The SHARC can be booted by reading data from an EPROM, by a host processor writing data through its external port, or by another processor writing data through its link ports.
The booting mode is configured in hardware by three pins: EBOOT, LBOOT and BMS.
Unlike other boot modes where control registers are initialized to meaningful values, the link port control register is initialized to zero but it is ignored during the initial booting process.