Analog Devices EE-63 Considerations for FLASH PROMS with Timing Requirements Application Note

About this manual

This document is an Engineer-to-Engineer Note (EE-63) from Analog Devices regarding the use of their DSP components and development tools. It specifically addresses technical questions about timing requirements between the RESET signal and the /BMS (Boot Mode Select) signal for SHARC processors.

The note provides specific cycle counts for when the /BMS pin will be asserted after the RESET pin is deasserted, distinguishing between different processor models: the 21060/60L, 21062/62L, and 21061/61L series require a minimum of five cycles (RESET high to /BMS low), while the 21065L requires only three cycles. A cycle is defined as one CLKIN period.

What's inside

• Engineer To Engineer Note
• FLASH PROMS Timing Requirements
• RESET and BMS timing
• SHARC DSP components
• 21065L specifications

Frequently asked questions

What is the minimum time between the rising edge of RESET and the falling edge of /BMS for the 21060/60L, 21062/62L, and 21061/61L processors?

If the first cycle that RESET is deasserted (goes high) is cycle #1, then /BMS will be asserted (go LOW) in cycle #6.

What is the minimum time between the rising edge of RESET and the falling edge of /BMS for the 21065L processor?

If the first cycle that RESET is deasserted (goes high) is cycle #1, then /BMS will be asserted (go LOW) in cycle #4.