ANALOG DEVICES EE-143 Understanding DMA on the ADSP-TS101 Manual

About this manual

This document serves as an Engineer-to-Engineer note detailing various forms of Direct Memory Access (DMA) on the ADSP-TS101 TigerSHARC family of processors. It explains how the on-chip DMA controller allows data transactions to occur as background tasks, freeing the processor core for signal processing operations. The text outlines the 14 available DMA channels, their priorities, and the specific types of data transfers supported, such as internal to external memory and link port I/O transfers.

What's inside

• Introduction
• DMA Channels
• Transfer Control Block
• TCB Registers
• DMA Demonstrations
• SDRAM Example
• Link Port Example
• Chaining Example
• Ext_mem_to_link Example

Specifications

Frequently asked questions

What is the primary function of the DMA controller?

It allows data transactions to take place as a background task, freeing up the processor core for signal processing operations.

How many DMA channels are dedicated to external memory devices?

Four channels are dedicated to external memory devices.

What is the size of the Transfer Control Block (TCB)?

The TCB is a quad word register consisting of four 32-bit registers.