This document describes how to use Analog Devices DSPs, processors, and development tools, as well as the transition times of Blackfin® processors between different operating modes.
This document describes the power mode transition times for Blackfin processors, specifically covering transitions between Full-on, Active, Sleep, Deep-Sleep, and Hibernate modes. It explains the conditions under which these transitions occur and the specific clock cycles required to move into and out of each state. The measurements were taken on an ADSP-BF533 EZ-KIT Lite evaluation system.
The note also discusses the process for changing the PLL VCO frequency, including the bypass switch operation to avoid glitches and the timing associated with the PLL lock counter. This information assists system designers in balancing power saving requirements with performance constraints.
It takes approximately 10 CCLK clocks to execute the first instruction following IDLE because the ten-stage instruction pipeline must be flushed and refilled.