Analog Devices SHARC Processors UART Port Controller Application Note

This file describes the characteristics and programming methods of the UART port controller of the SHARC processor

Brand: Analog Devices
Document type: Application Note
Language: English
Pages: 7
File format: PDF
File size: 115 KB
Published: 03 August, 2012
Updated: 30 September, 2023
Models: ADSP-21367, ADSP-21368, ADSP-21369, ADSP-21371, ADSP-21375
MD5 checksum: B8A49DFB5A8A9AE55695C82D737711B1
PDF: Analog Devices SHARC Processors UART Port Controller Application Note PDF

About this manual

This Engineer-to-Engineer Note provides technical details on using the Universal Asynchronous Receiver Transmitter (UART) port controller found in specific Analog Devices SHARC® processors. It covers UART data frame structures, synchronization effects, and interface requirements for EIA-232E communication.

The document outlines programming techniques required to configure full-duplex DMA operations, handle UART interrupts, and establish communication with a PC. It includes examples of assembly code for setting baud rates and configuring line control registers.

What's inside

Introduction
UART Data Frame
Synchronization Effects
UART External Interface
EIA-21368 Processors
Programming Techniques
Full-Duplex DMA
UART Interrupts

Specifications

Supported Processor Models	ADSP-21371, ADSP-21375, ADSP-21367, ADSP-21368, ADSP-21369
UART Count per Processor	Two for 21367/21368/21369; One for 21371/21375
Data Frame Length Range	7 to 12 bits
Baud Rate Derivation Source	Processor's peripheral clock

Frequently asked questions

What are the supported SHARC processor models?

The document covers ADSP-21371, ADSP-21375, ADSP-21367, ADSP-21368, and ADSP-21369.

How many UARTs do the ADSP-21367/21368/21369 processors have?

They have two UARTs.

What is the range of data bits in a UART frame?

The total length of data bits may vary from 5 to 8.

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