This document describes the power-decoupling requirements for boards that contain SHARC® processors. It is intended to help system designers to calculate the total supply decoupling capacitance, choose the capacitor values, and place the capacitors for optimal results.
This Engineer-to-Engineer Note (EE-253) describes power-decoupling requirements for boards containing SHARC processors. It is intended to help system designers calculate the total supply decoupling capacitance, choose capacitor values, and place capacitors for optimal results to avoid intermittent hardware problems caused by power supply noise.
The objective is to keep peak noise voltage amplitudes under 82.5 mV for 3.3V supplies (under 30 mV for 1.2V supplies) over the full frequency spectrum.
A typical voltage regulator precision is ±2.5%, so the peak noise voltage should not exceed 2.5% of the supply voltage.