This document introduces the products and services of ALTERA Corporation and explains its trademarks. It also describes the features and characteristics of the Quartus II TimeQuest Timing Analyzer.
The Quartus II TimeQuest Timing Analyzer is a powerful ASIC-style timing analysis tool that validates the timing performance of all logic in your design. It uses an industry-standard constraint, analysis, and reporting methodology to verify timing paths within Altera FPGA designs.
To run the analyzer, users can utilize the GUI via the Tools menu or execute command-line interfaces such as 'quartus_sta' for scripting integration. The document details a recommended design flow involving project creation, initial compilation, specification of timing requirements, full compilation, and verification.
Type the command 'quartus_sta' at the command prompt.
The Quartus II software assigns a default frequency of 1 GHz for clocks that have not been constrained.
Type 'quartus_sta -s@' at a system command prompt.