Altera Nios II Hardware Development Tutorial

About this manual

This document is a tutorial introducing the system development flow for the Altera Nios II processor. It guides users through creating a custom Nios II system by analyzing requirements, defining the system in Qsys, integrating it into a Quartus II project, and developing software using the Nios II Software Build Tools for Eclipse.

What's inside

• Nios II Hardware Development Design Example
• Software and Hardware Requirements
• OpenCore Plus Evaluation
• Nios II System Development Flow
• Analyzing System Requirements
• Defining and Generating the System in Qsys
• Integrating the Qsys System into the Quartus II Project
• Developing Software with the Nios II SBT for Eclipse

Frequently asked questions

Can I build the design example without a license?

Yes, you can perform this tutorial on hardware without a license using Altera's free OpenCore Plus evaluation feature.

What components are included in the design example Nios II system?

The system contains a Nios II/s processor core, on-chip memory, a timer, a JTAG UART, PIO pins to control LEDs, and a system identification component.

What are the minimum logic element requirements for an FPGA used in this tutorial?

The FPGA must contain a minimum of 2500 logic elements (LE) or adaptive look-up tables (ALUT).

What is the maximum recommended clock frequency for most development boards?

Frequencies of 50 MHz or less should work for most boards.