Altera MAX V Device Handbook

About this manual

This document serves as a comprehensive technical reference for the Altera MAX V device family. It details the core architecture, including Logic Array Blocks (LABs), Logic Elements (LEs), and MultiTrack interconnects, explaining their functional descriptions and operating modes such as Normal Mode and Dynamic Arithmetic Mode.

The handbook also covers system integration capabilities, including hot socketing specifications for 5.0-V compatibility, JTAG boundary-scan testing support per IEEE Std. 1149.1, and in-system programmability features. Additionally, it provides extensive information on the User Flash Memory (UFM) block, detailing its organization, access methods via I2C, SPI, and parallel interfaces, and programming sequences.

What's inside

• MAX V Device Family Overview
• MAX V Architecture
• DC and Switching Characteristics
• Hot Socketing and Power-On Reset
• Using MAX V Devices in Multi-Voltage Systems
• JTAG and In-System Programmability
• User Flash Memory (UFM)
• JTAG Boundary-Scan Testing

Specifications

Frequently asked questions

What is the MAX V device family?

The MAX V device family is a group of semiconductor products that includes features relating to the device core.