This document is a configuration manual published by Altera Corporation. It introduces the configuration methods of Altera products, including security and remote system upgrades.
This document serves as a comprehensive guide for configuring Altera Field-Programmable Gate Arrays (FPGAs). It covers configuration schemes such as Fast Passive Parallel (FPP), Active Serial (AS), Passive Serial (PS), and JTAG for multiple device families including Stratix V, IV, III, II, GX, Cyclone IV, III, II, I, Arria II, GX, APEX II, 20KE, 20KC, Mercury, ACEX 1K, and FLEX 10K.
The handbook details the procedures for executing configuration schemes, setting option pins, and managing power-on reset circuits. It also explains advanced features available in specific devices, such as real-time data decompression, design security via bitstream encryption, and remote system upgrades.
| Supported Configuration Voltages | 1.8, 2.5, and 3.0 V |
|---|---|
| Fast POR Delay Minimum | 4ms |
| Fast POR Delay Maximum | 12 ms |
| Standard POR Delay Minimum | 100 ms |
| Standard POR Delay Maximum | 300 ms |
Yes, Stratix V devices can receive a compressed configuration bitstream and decompress this data in real-time.
The Vccpp pin is a dedicated programming power supply that must be connected to 3.0 V or 2.5 V to power the I/O pre-drivers and JTAG I/O pins.