Key facts
- Brand
- Altera
- Model
- ACEX 1K
- Category
- Other Electronics
- Documents
- 4
- Languages
- EN
- Last added
- 2012-08-01
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Altera FPGA Configuration Handbook
This document serves as a comprehensive guide for configuring Altera Field-Programmable Gate Arrays (FPGAs). It covers configuration schemes such as Fast Passive Parallel (FPP), Active Serial (AS), Passive Serial (PS), and JTAG for multiple device families including Stratix V, IV, III, II, GX, Cyclone IV, III, II, I, Arria II, GX, APEX II, 20KE, 20KC, Mercury, ACEX 1K, and FLEX 10K.
The handbook details the procedures for executing configuration schemes, setting option pins, and managing power-on reset circuits. It also explains advanced features available in specific devices, such as real-time data decompression, design security via bitstream encryption, and remote system upgrades.
Altera ACEX 1K specifications
| Supported Configuration Voltages | 1.8, 2.5, and 3.0 V |
|---|---|
| Fast POR Delay Minimum | 4ms |
| Fast POR Delay Maximum | 12 ms |
| Standard POR Delay Minimum | 100 ms |
| Standard POR Delay Maximum | 300 ms |
All Altera ACEX 1K documents by type
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Ratings, dimensions and ordering codes, for selection and design work.
How to use the product for one specific task, with worked examples.
Questions answered in these manuals
Can Stratix V devices receive compressed configuration data?
Yes, Stratix V devices can receive a compressed configuration bitstream and decompress this data in real-time.
What is the purpose of the Vccpp pin in Stratix V devices?
The Vccpp pin is a dedicated programming power supply that must be connected to 3.0 V or 2.5 V to power the I/O pre-drivers and JTAG I/O pins.
Do Stratix V devices support design security?
Yes, design security using configuration bitstream encryption is available in Stratix V devices.
From: Altera FPGA Configuration Handbook (Complete Two-Volume Set)
What is the minimum and maximum delay for the fast power-on reset in Stratix V devices?
The fast power-on reset delay ranges from a minimum of 4 ms to a maximum of 12 ms.
From: Altera FPGA Configuration Handbook (Complete Two-Volume Set)
What is the maximum number of RAM bits in an ACEX 1K device?
An ACEX 1K device can contain up to 49,152 RAM bits.
From: Altera ACEX 1K Programmable Logic Device Family Datasheet
What voltage does the ACEX 1K core operate at?
The core operates with a 2.5‑V internal supply voltage.
From: Altera ACEX 1K Programmable Logic Device Family Datasheet