This document introduces the architecture and functional characteristics of the Altera Stratix II series devices.
The document provides a functional description of the Stratix II architecture, which utilizes a two-dimensional row- and column-based structure to implement custom logic. It details how signal interconnects link Logic Array Blocks (LABs), various memory block structures including M512 RAM, M4K RAM, and M-RAM blocks, and Digital Signal Processing (DSP) blocks.
The text further explains the specific resources available within each LAB, such as Adaptive Logic Modules (ALMs), registers, adders, and chains. It also covers I/O elements supporting various standards like DDR SDRAM and LVDS, along with high-speed serial interface channels.
| M512 RAM width | up to 18-bits wide |
|---|---|
| M4K RAM width | up to 36-bits wide |
| M-RAM width | up to 144-bits wide |
| DSP block multiplier size | 36 x 36-bit |
| High-speed serial interface speed | up to 1 Gbps |
M512 RAM blocks operate at up to 500 MHz.
A DSP block can implement eight 9 x 9-bit, four 18 x 18-bit, or one 36 x 36-bit multiplier.
High-speed serial interface channels support data transfer at up to 1 Gbps.