This manual introduces the I/O features of Altera Stratix III FPGA devices, including single-ended, non-voltage-referenced, voltage-referenced I/O standards, low-voltage differential signaling (LVDS), reduced swing differential signal (RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and stub series terminated logic (SSTL), single data rate (SDR) and half data rate (HDR—half frequency and twice data width of SDR) input and output options, and the number of I/O pins, maximum speed, etc.