This manual introduces the I/O features of Altera Stratix III FPGA devices, including single-ended, non-voltage-referenced, voltage-referenced I/O standards, low-voltage differential signaling (LVDS), reduced swing differential signal (RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and stub series terminated logic (SSTL), single data rate (SDR) and half data rate (HDR—half frequency and twice data width of SDR) input and output options, and the number of I/O pins, maximum speed, etc.
The document describes the Stratix III I/O banks as being designed for ease of use and rapid system integration. It highlights independent modular structures with a common bank structure to facilitate vertical migration and high-speed data transfer capabilities up to 1.6 Gbps.
Key features include support for various single-ended, non-voltage-referenced, and voltage-referenced I/O standards such as LVDS, RSDS, mini-LVDS, HSTL, and SSTL. The device offers programmable output current strength, slew rate, delay, bus-hold, pull-up resistors, and on-chip termination options.
| Max LVDS Channels (Full Duplex) | 132 Tx + 132 Rx |
|---|---|
| Supported Voltage Levels | 3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V |
| Max I/O Banks | Up to 24 |
The device supports single-ended, non-voltage-referenced, and voltage-referenced I/O standards including LVDS, RSDS, mini-LVDS, HSTL, and SSTL.
Yes, the device includes a programmable output current strength feature.