MPC2002 and MPC2003 are Motorola's 256KB and 512KB BurstRAM secondary cache modules for PowerPC systems. The modules are configured as 32K x 72 and 64K x 72 bits in a 136-pin dual read single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0-PD2 are reserved for density and speed identification.
This document provides technical specifications for the MPC2002 and MPC2003 modules, which are 256KB and 512KB BurstRAM secondary cache modules designed for PowerPC 60x processors. The modules are configured as 136-pin dual readout single inline memory modules (DIMMs) and utilize Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs.
| Capacity | 256KB or 512KB |
|---|---|
| Package Type | 136 pin dual readout single inline memory module (DIMM) |
| Power Supply | Single 5 V+5% Power Supply |
| Clock Rates | 66 MHz, 60 MHz, 50MHz |
| Operating Temperature | 0 to +70 °C |
The modules are designed to interface with the PowerPC 60x bus.
They use four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs.
Yes, all inputs and outputs are TTL compatible.