This document is a technical overview of the PowerPC 604e microprocessor, a new product developed in collaboration between Motorola and IBM. It describes the features and major functional components of the processor.
This document provides an overview of the PowerPC 604e microprocessor features, including a block diagram showing major functional components. It explains how the 604e implementation complies with the PowerPC architecture definition for 32-bit addressing and floating-point data types.
The MPC604e is a superscalar processor capable of issuing four instructions simultaneously, with up to seven instructions finishing execution in parallel via seven independent execution units. Key features include separate memory management units, on-chip caches, and support for demand-paged virtual memory address translation.
| Data Bus Width | 64-bit |
|---|---|
| Address Bus Width | 32-bit |
| Instruction Issue Capability | Four instructions simultaneously |
| Execution Units Count | Seven |
| Instruction Cache Size | 32-Kbyte |
| Data Cache Size | 32-Kbyte |
| Process Technology | 2.5-V CMOS |
Vdd and AVdd must be tied to 2.5 Vdc, while OVdd must be tied to 3.3 Vdc.
It is an implementation of the PowerPC family of reduced instruction set computer (RISC) microprocessors.
The Vdd and AVdd pins must be tied to 2.5 Vdc, and the OVdd pin must be tied to 3.3 Vdc.
The processor is capable of issuing four instructions simultaneously, and as many as seven instructions can finish execution in parallel.