This document provides an overview of a new product developed by Motorola and IBM, introducing the features and characteristics of the PowerPC 603e microprocessor, as well as its compliance with the PowerPC architecture specification.
This document provides an overview of the Motorola MPC603e microprocessor, a low-power implementation of the PowerPC family. It details the processor's features, including its superscalar architecture, five independent execution units, and integrated power management capabilities. The text describes the block diagram and operational flow of the major functional components.
| Architecture | 32-bit portion of the PowerPC architecture |
|---|---|
| Power Modes | nap, doze, sleep, and dynamic power management |
| Instruction Throughput | As many as three instructions issued and retired per clock |
| Data Cache | 16-Kbyte, four-way set-associative |
| Instruction Cache | 16-Kbyte, four-way set-associative |
It is the PowerPC 603e microprocessor.
International Business Machines Corporation (IBM).