This is the PFCM design guide of FAIRCHILD SEMICONDUCTOR, which introduces the PFCM system configuration, protection circuits, design examples, experimental results.
The document serves as a design guide for the Fairchild PFCM (Power Factor Correction Module) system. It details typical system configurations, emphasizing the need for inrush-current prevention circuits due to large DC link capacitance. The text explains how the PFCM, mini-SPM, and control IC can share a single ground stage while managing surge voltages through proper wiring and snubber capacitors.
| Switching Frequency | 40 kHz |
|---|---|
| Maximum Input Voltage | 264 Vac |
| Output Max Power | 5000 W |
| Nominal Output Voltage | 380 Vdc |
| OVP Level 1 Threshold | 420 V |
| OCP Level 1 Current | 40 A |
The recommended switching frequency (Fsw) for the design example is 40 kHz.
When an over current situation occurs, the PFCM stops operating and generates a fault-out signal for a set duration before resuming operation.
It is required due to the large DC link capacitance to prevent damage from initial charging currents.