This document describes the features and functions of the Philips Semiconductors 74F1763 Intelligent DRAM Controller (IDC), including DRAM signal timing generator, automatic refresh circuitry, selectable row address hold and RAS precharge times, etc. The controller is designed for controlling 1 MBit DRAMs and supports intelligent burst-mode refresh after page-mode access cycles. The document also introduces some improved features of the product, such as page-mode access, selectable RAS precharge time, and row-address hold time to fit different DRAMs.
The Philips 74F1763 is a 1 MBit, single-port Intelligent DRAM Controller (IDC) designed to interface with dynamic RAMs. It features automatic signal timing, address multiplexing, and refresh control, with a maximum clock frequency of 100 MHz. The device supports page mode accesses and includes a burst refresh monitor to ensure complete refreshing after lengthy page-mode access cycles.
The controller allows users to select row address hold and RAS precharge times to fit specific DRAMs. It contains automatic signal timing, address multiplexing, and refresh control required for interfacing with dynamic RAMs. Additional features include an Address Latch Enable (ALE) input for latched or unlatched address options and a negative true, tri-stated DTACK output.
| Maximum Clock Frequency | 100 MHz |
|---|---|
| Operating Temperature | 0°C TO 70°C |
| Package Type | 48-pin Plastic DIP |
| Typical Supply Current | 150 mA |
The controller operates with a maximum clock frequency of 100 MHz.
The typical maximum supply current is 150 mA when operating at 100 MHz.
If the PRECHRG input is low, RAS must remain high for at least 4 CP clock cycles.