The 74F173 is a high speed 4-bit parallel load register with clock enable control, 3-state buffered outputs, and master reset (MR) function
The Philips 74F173 is a high-speed 4-bit parallel load register featuring edge-triggered D-type flip-flops with clock enable control and master reset. It includes 3-state buffered outputs controlled by independent output enable inputs, allowing for bus interfacing without affecting clock and reset operations. The device supports a maximum clock frequency of 125 MHz and offers a sinking capability of 48 mA.
| Low-level output current | 48 mA |
|---|---|
| Operating temperature range | 0 to +70 °C |
The master reset is an active-high asynchronous input that resets all four flip-flops independently of any other input condition.
The buffers are controlled by a 2-input NOR gate; when both output enable inputs are low, data is presented at the output, otherwise outputs are high impedance.