Toshiba TC74HC4024AP/AF 7-Stage Binary Counter Datasheet


Toshiba TC74HC4024AP/AF 7-Stage Binary Counter Datasheet - cover page
Brand
Toshiba
Category
Digital
Document type
Datasheet
Language
English
Pages
5
File format
PDF
File size
213 KB
Published
12 June, 2012
Updated
12 June, 2012
MD5 checksum
85A323EFA96D91E88620E8F94305F870

About this manual

The TC74HC4024A is a high-speed CMOS 7-stage binary counter fabricated with silicon gate CMOS technology. It achieves high-speed operation similar to equivalent LSTTL while maintaining low power dissipation. A negative transition on the CK input brings one increment to the counter, and a high level at the CLR input resets the counter to the all low level state. All divided output stages are provided, with the last stage offering a 1/128 divided frequency.

What's inside

  • Features
  • Pin Assignment
  • Truth Table
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • DC Electrical Characteristics
  • Timing Requirements
  • AC Electrical Characteristics
  • Outline Drawings

Specifications

Supply Voltage Range2V to 6V
Quiescent Supply Current4uA (Max.) at Ta = 25°C
Output Drive Capability10 LSTTL Loads
Operating Temperature-40°C to +85°C
Storage Temperature-65°C to +150°C
Input Leakage Current+1.0 uA (Max.) at Vcc = 6.0V

Frequently asked questions

What is the function of the CLR input?

A high level at the CLR input accomplishes the reset function, resetting the counter to the all low level state.

How many stages does the counter have?

The TC74HC4024 is a 7-stage binary counter.

Is the device compatible with the 4024B?

Yes, the pin and function are compatible with the 4024B.

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