Data Delay Devices PDU1016H 4-Bit ECL-Interfaced Programmable Delay Line Datasheet

The PDU1016H is a 4-bit, ECL-interfaced digitally programmable delay line that can be digitally programmed in 16 delay steps. The product features monotonic delay-versus-address variation, precise and stable delays, and fully 10KH-ECL interfaced and buffered inputs and outputs.


Data Delay Devices PDU1016H 4-Bit ECL-Interfaced Programmable Delay Line Datasheet - cover page
Brand
Data Delay Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
5
File format
PDF
File size
50 KB
Published
11 June, 2012
Updated
30 September, 2023
MD5 checksum
45E14286869C7CF3C9C2F11C763CB6F5

About this manual

The PDU1016H-series device is a 4-bit digitally programmable delay line featuring ECL interfacing and buffering. It offers 16 programmable delay steps with monotonic delay-versus-address variation, allowing precise and stable delays. The device fits a 32-pin DIP socket and is available in various packages including DIP and SMD.

What's inside

  • Functional Description
  • Pin Descriptions
  • Series Specifications
  • Application Notes
  • Address Update
  • Input Restrictions
  • AC Characteristics
  • Absolute Maximum Ratings
  • DC Electrical Characteristics
  • Package Dimensions

Specifications

Total programmed delay tolerance5% or 1ns, whichever is greater
Operating temperature0° to 70° C
Temperature coefficient100PPM/°C
Power Dissipation615mw typical (no load)
Minimum pulse width20% of total delay

Frequently asked questions

What is the formula for the delay of the PDU1016H?

The delay (TDa) depends on the address code (A) according to the formula: TDa = TDp + Tinc * A.

What is the range of incremental delay for the PDU1016H?

The incremental delay can range from 0.5ns through 100ns, inclusively.

What happens when the enable pin (ENB) is brought HIGH?

When the ENB signal is brought HIGH, the output (OUT) is forced into a LOW state.

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