This document describes the features of the 3D7303 Monolithic Triple Fixed Delay Line produced by DATA DELAY DEVICES, INC. The product utilizes all-silicon, low-power CMOS technology and has TTL/CMOS compatible inputs and outputs. It is vapor phase, IR, and wave solderable, as well as auto-insertable (DIP pkg.). The product offers low ground bounce noise, leading- and trailing-edge accuracy, a delay range of 10 through 500ns, a delay tolerance of 2% or 1.0ns, temperature stability of ±3% typical (0C-70C), and Vdd stability of ±1% typical (4.75V-5.25V). The product can be used as a drop-in replacement for hybrid delay lines and is available in 14-pin DIP and surface mount 8-pin SOIC packages.
The 3D7303 family consists of three matched, independent CMOS delay lines packaged in an 8‑pin DIP or 8‑pin SOIC. Each line reproduces the input signal without inversion, shifted in time according to the selected delay value. The device is TTL‑ and CMOS‑compatible and can drive ten 74LS‑type loads while maintaining both rising‑ and falling‑edge accuracy.
Key features include low ground‑bounce noise, temperature stability of +3 % typical over 0 °C‑70 °C, VDD stability of +1 % typical over 4.75 V‑5.25 V, and a minimum input pulse width of 20 % of the total delay. Detailed electrical specifications, absolute maximum ratings, and test setup procedures are provided for design verification.
| Delay range | 10 through 500 ns |
|---|---|
| Delay tolerance | 2 % or 1.0 ns |
| Temperature stability | +3 % typical (0 °C‑70 °C) |
| VDD stability | +1 % typical (4.75 V‑5.25 V) |
| Minimum input pulse width | 20 % of total delay |
| Supply voltage range | -0.3 V to +7.0 V |
| Static supply current | 30 mA |
| High‑level input voltage | 2.0 V |
| Low‑level input voltage | 0.8 V |
| Output rise/fall time | 2 ns |
The 3D7303 provides a fixed delay that can be set anywhere from 10 ns to 500 ns.
Each package contains three matched, independent delay lines.
The device operates from a nominal 4.75 V to 5.25 V, with an absolute maximum rating of 7 V.