This document is a data manual for XIO1100, providing information about the features and characteristics of the product.
The XIO1100 is a PCI Express Physical Layer (PHY) device that interfaces between the Media Access Control (MAC) layer and the serial link. It supports both 16-bit Single Data Rate (SDR) and 8-bit Double Data Rate (DDR) modes via a configurable TI-PIPE interface.
The device handles 8B/10B encoding, decoding, scrambling, and unscrambling of data. It features selectable reference clocks for transmit and receive operations and includes power management capabilities to support low-power states.
| PCI Express Compliance | 1.1 Compliant |
|---|---|
| Interface Modes | 16-bit SDR or 8-bit DDR |
| Clock Frequencies | 100 MHz, 125 MHz |
| Package Type | 100-Pin MicroStar BGA |
| Operating Voltage | 3.3/1.8/1.5 V |
It is a modified version of the Intel PIPE interface used by the XIO1100 to connect the MAC to the serial link.
The XIO1100 is a PCI Express PHY that interfaces the Media Access Layer to a PCI Express serial link.
The device supports selectable reference clocks of 100 MHz or 125 MHz.
The device operates within a temperature range of 0°C to 70°C.