Texas Instruments CD4027B CMOS Dual J-K Master-Slave Flip-Flop Datasheet

This document describes the features and characteristics of the CD4027B products, as well as supplier information for different package types.


Texas Instruments CD4027B CMOS Dual J-K Master-Slave Flip-Flop Datasheet - cover page
Brand
Texas Instruments
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
12
File format
PDF
File size
524 KB
Published
08 June, 2012
Updated
29 September, 2023
Model
CD4027B
MD5 checksum
7F67B285699619D9C816C8E9B34875E3

About this manual

The CD4027B is a monolithic integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. It features provisions for individual J, K, Set, Reset, and Clock input signals, with buffered Q and Q outputs. The device operates at high voltage levels up to 20V and supports medium-speed operation with a typical clock toggle rate of 16 MHz.

What's inside

  • Features
  • Applications
  • Maximum Ratings
  • Recommended Operating Conditions
  • Static Electrical Characteristics
  • Dynamic Electrical Characteristics

Frequently asked questions

What is the maximum supply voltage rating?

The device has a high-voltage rating of up to +20V.

How many flip-flops are contained in the chip?

It contains two identical complementary-symmetry J-K master-slave flip-flops.

Are the Set and Reset functions dependent on the clock?

No, they are independent of the clock.

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