Integrated Device Technology IDT72255/IDT72265 CMOS Supersync FIFO Datasheet

This datasheet introduces the features of IDT72255 and IDT72265, including storage capacity, read/write clock cycle, retransmit capability, auto power down, master reset, partial reset, empty, full, half-full flag, programmable almost empty and almost full flag, independent read and write clock, select IDT standard timing or first word fall through timing.


Integrated Device Technology IDT72255/IDT72265 CMOS Supersync FIFO Datasheet - cover page
Brand
Integrated Device Technology
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
30
File format
PDF
File size
402 KB
Published
06 June, 2012
Updated
01 October, 2023
MD5 checksum
ACA3E257C2953BDA445408B8AF5A2288

About this manual

The IDT72255/IDT72265 are monolithic CMOS FIFO memories with clocked read and write controls designed for data buffering in applications such as optical disk controllers, local area networks (LANs), and inter-processor communication. The devices offer 8,192 x 18-bit storage capacity for the IDT72255 and 16,384 x 18-bit storage capacity for the IDT72265.

What's inside

  • Features
  • Description
  • Functional Block Diagram
  • Pin Configurations
  • Pin Description
  • Timing Modes

Specifications

Storage Capacity (IDT72255)8,192 x 18-bit
Storage Capacity (IDT72265)16,384 x 18-bit
Read/Write Cycle Time10ns
Access Time8ns
Input/Output Port Width18-bit
Operating Temperature Range-40°C to +85°C

Frequently asked questions

What are the storage capacities of the IDT72255 and IDT72265?

The IDT72255 has an 8,192 x 18-bit capacity while the IDT72265 has a 16,384 x 18-bit capacity.

What is the read/write cycle time for these FIFOs?

The devices feature a 10ns read/write cycle time and an 8ns access time.

Are military temperature ranges available for these parts?

Yes, the devices are tested to military electrical specifications in addition to industrial temperature ranges.

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