This document describes the features and characteristics of Actel Corporation's 54SX family FPGA products. These products offer leading edge performance, including 320 MHz internal performance, 3.7 ns clock-to-out delay, 0.1 ns input setup time, etc. They also feature 12,000 to 48,000 system gates, up to 249 user-programmable I/O pins, up to 1080 flip-flops, etc. Additionally, these products support 66 MHz PCI bus, integration of CPLD and FPGA, single chip solution, 3.3V operation, etc. They also offer user-controllable deterministic timing, unique in-system diagnostic and debug capability, boundary scan testing in compliance with IEEE standard 1149.1, secure programming technology, etc.
The Actel 54SX Family FPGAs feature a unique 'sea-of-modules' architecture that integrates combinatorial cells (C-cells) and register cells (R-cells) with routing resources between metal layers. This design eliminates traditional channels, allowing for an uninterrupted grid of logic modules which simplifies design time and reduces costs.
Key performance features include up to 320 MHz internal performance, a clock-to-out delay as low as 3.7 ns, and input set-up times down to 0.1 ns. The family offers various device capacities ranging from 8,000 to 48,000 system gates with options for commercial, industrial, and military temperature grades.
| Internal Performance | 320 MHz |
|---|---|
| Clock-to-Out (Pin-to-Pin) | 3.7 ns |
| Input Set-Up | 0.1 ns |
| Clock Skew | 0.25 ns |
| System Gates Range | 12,000 to 48,000 |
| User-Programmable I/O Pins | Upto 249 |
| Flip-Flops | Up to 1080 |
The maximum internal performance is 320 MHz.
Yes, specific models in the family are PCI compliant.