Update: 30 September, 2023
The 54SX family of FPGAs is a leading-edge FPGA with an internal performance of up to 320 MHz, a clock-to-output (pin-to-pin) delay of 3.7 ns, an input setup time of 0.1 ns, and a clock skew of 0.25 ns. The series has 12,000 to 48,000 system gates, up to 249 user-programmable I/O pins, up to 1080 dedicated flip-flops, and is manufactured using a 0.35µ CMOS process. The series also features 66 MHz PCI, CPLD and FPGA integration, a single-chip solution, 100% resource utilization and 100% pin locking, 3.3V operation and 5.0V input tolerance, very low power consumption, deterministic, user-controllable timing, Silicon Explorer II's unique In-System diagnostic and debug capability, boundary scan testing in compliance with IEEE Standard 1149.1 (JTAG), and secure programming technology that prevents reverse engineering and design theft.
File format: PDF
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MD5 Checksum: 5133C90F530A7C8A23F2E3A5F8C24A8E
Publication date: 10 May, 2012
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PDF Link: Actel 54SX Family FPGAs DATA SHEET PDF