The eX family of FPGAs is a low-cost solution for low-power, high-performance designs. The inherent low power attributes of the antifuse technology, coupled with an additional low static power mode, make these devices ideal for high-performance, low-power applications.
The eX Family FPGAs are low‑power, high‑performance antifuse devices offering 3,000 to 12,000 system gates, up to 132 user‑programmable I/O pins, and clock‑to‑out times as fast as 3.9 ns. Features include hot‑swap capability, mixed‑voltage operation (2.5 V, 3.3 V, 5.0 V), and built‑in diagnostic support via Silicon Explorer II.
The handbook details device architecture (R‑cells, C‑cells, clusters, and SuperClusters), routing resources (FastConnect, DirectConnect), clock networks, power requirements, low‑power mode, boundary‑scan testing, and supported development tools (Actel Designer Series and Libero). Ordering information, package options, and electrical specifications for the eX64, eX128, and eX256 parts are also provided.
| System Gates | 3,000 to 12,000 |
|---|---|
| Maximum User I/Os | 132 |
| Clock‑to‑Out (Pad‑to‑Pad) | 3.9 ns |
| Internal Performance | 350 MHz |
| Process Technology | 0.224 µm CMOS |
| Hot‑Swap Capability | Yes |
| Low Power Standby Current (eX64) | 100 µA |
| Supported Design Tools | Actel Designer Series, Libero |
The eX devices achieve a clock‑to‑out (pad‑to‑pad) delay of 3.9 ns.
The eX256 device provides up to 132 user‑programmable I/O pins.
Yes, the eX family is hot‑swap compliant.
Actel Designer Series and Libero tools fully support the eX devices.