Update: 30 September, 2023
The X25C02 is a CMOS 2048-bit serial E2PROM, internally organized as 256 x 8. The X25C02 features a serial interface and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25C02 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25C02 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25C02 disabling all write attempts, thus providing a mechanism for limiting end user capability of altering the memory. The X25C02 utilizes Xicor’s patented design and manufacturing techniques, including advanced automated processes, to ensure outstanding performance and reliability.
File format: PDF
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MD5 Checksum: 9E7B6B8F50864112A150C1DD7CCD0C51
Publication date: 04 June, 2012
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PDF Link: XICOR X25C02 DATA SHEET PDF