The DS90CF384A/DS90CF364A is a +3.3V LVDS Receiver that converts 24-bit or 18-bit LVDS data streams (up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28-bit or 21-bit CMOS/TTL data (24-bit or 18-bit RGB and 4-bit or 3-bit Hsync, Vsync, DE and CNTL).
The DS90CF384A and DS90CF364A are 3.3 V LVDS receivers that convert high‑speed LVDS data streams into parallel CMOS/TTL outputs for 24‑bit and 18‑bit flat‑panel displays.
Both devices support 20‑65 MHz shift clocks, provide low power consumption (<250 mW typical), include ESD protection >7 kV, and are offered in low‑profile 56‑lead (384A) or 48‑lead (364A) TSSOP packages.
| Maximum LVDS throughput (DS90CF384A) | Up to 1.8 Gbps (227 MB/s) |
|---|---|
| Maximum LVDS throughput (DS90CF364A) | Up to 1.3 Gbps (170 MB/s) |
| Typical power consumption (65 MHz) | <250 mW (typ) |
| Power‑down mode consumption | <200 µW (max) |
| ESD rating | >7 kV (HBM), >700 V (EIAd) |
| Package (DS90CF384A) | 56‑lead TSSOP (MTD56) |
| Package (DS90CF364A) | 48‑lead TSSOP (MTD48) |
It can handle up to 1.8 Gbps (227 MB/s) of LVDS data.
Typical power consumption is less than 250 mW at 65 MHz.
The DS90CF384A is offered in a 56‑lead TSSOP (MTD56) package, while the DS90CF364A uses a 48‑lead TSSOP (MTD48) package.