Update: 01 October, 2023
The 74LVQ280 is a low voltage CMOS 9 bit parity generator fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. It is composed of nine data inputs (A to I) and odd/ even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ΣODD output is kept high and ΣEVEN output low. Conversely, when the number of high level is even, ΣEVEN output is kept high and ΣODD low. The IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
File format: PDF
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MD5 Checksum: B080ABC6D3FAD03A88463A64E2962F47
Publication date: 10 May, 2012
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PDF Link: ST 74LVQ280 9 BIT PARITY GENERATOR handbook PDF