The 74LVQ280 is a low voltage CMOS 9 bit parity generator fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. It is composed of nine data inputs (A to I) and odd/ even parity outputs (ΣODD and ΣEVEN). The nine data inputs control the output conditions. When the number of high level input is odd, ΣODD output is kept high and ΣEVEN output low. Conversely, when the number of high level is even, ΣEVEN output is kept high and ΣODD low. The IC generates either odd or even parity making it flexible application. The word-length capability is easily expanded by cascading. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
The 74LVQ280 is a low‑voltage CMOS 9‑bit parity generator designed for 3.3 V applications. It provides nine data inputs and odd/even parity outputs, with TTL‑compatible levels, low power dissipation (2 µA typical) and high‑speed operation (8 ns typical propagation delay). The device includes ESD protection up to 2 kV and can drive transmission lines with 75 Ω impedance.
The datasheet lists absolute maximum ratings, recommended operating conditions, DC and AC electrical characteristics, propagation delays, input capacitance, and mechanical dimensions for both SOP and TSSOP packages. It also provides a test circuit and typical application notes.
| Operating voltage range | 2 V to 3.6 V |
|---|---|
| Typical supply voltage | 3.3 V |
| Output drive capability | 12 mA min |
The device operates from 2 V up to 3.6 V.
All inputs and outputs have 2 kV ESD immunity.
The IC is offered in SOP and TSSOP packages.