PSD835G2 is a configurable memory system on a chip for 8-bit microcontrollers.
The PSD835G2 is a configurable memory system on a chip designed for 8‑bit microcontrollers. It integrates up to 4 Mbit of primary flash, a 256 Kbit secondary flash for boot or data, and 64 Kbit SRAM, together with programmable logic and 52 configurable I/O pins.
The device supports In‑System Programming via a JTAG‑compliant serial port and In‑Application Re‑Programming, allowing firmware updates without MCU involvement. Power management, page register expansion, and a Windows‑based development tool (PSDsoft) complete the solution.
| Primary Flash Memory | up to 4 Mbit (8 uniform sectors) |
|---|---|
| Secondary Flash Memory | 256 Kbit (4 uniform sectors) |
| SRAM | up to 64 Kbit |
| Standby current | as low as 50 µA at 5 V |
| Flash erase/write cycles | minimum 100,000 cycles |
| PLD erase/write cycles | minimum 1,000 cycles |
| Package | 80‑pin TQFP |
| Supply voltage | 5 V ±10% |
The standby current can be as low as 50 µA for 5 V devices.