The SCxE6 family is a sub‑micron generation of channel‑less gate‑arrays based on Siemens' proven Megalogic process. It offers a 30% speed improvement over previous 1 µm technology and features an advanced 0.8 µm drawn gate‑length.
Design flow is fully supported by major workstation CAD tools such as Cadence, Mentor, Valid and Dassault. The Siemens Logic Design System (SLO5) integrates with industry‑standard software, enabling hierarchical design, cell pre‑placement and accurate delay calculation.
| Gate length | 0.8 µm |
|---|---|
| Available gates | 200,000 |
| Storage temperature range | -85 °C to 150 °C |
Full workstation support is provided for Cadence, Mentor, Valid and Dassault (Dasix) tools.
The SCxE6 devices offer a high packing density with about 200,000 available gates.
The devices can be stored from –85 °C up to 150 °C.