This data sheet provides details of the SPRS079E including its features, technical specifications and application instructions.
The TMS320VC5402 is a fixed‑point digital signal processor based on an advanced modified Harvard architecture with separate program and three data memory buses. It features a 40‑bit ALU, a 17 × 17‑bit parallel multiplier, two address generators, and on‑chip memory (4 K×16‑bit ROM, 16 K×16‑bit dual‑access RAM). The device supports high‑speed single‑cycle multiply‑accumulate operations and includes on‑chip peripherals such as two multichannel buffered serial ports, an enhanced 8‑bit host‑port interface, two 16‑bit timers, and a six‑channel DMA controller.
The DSP is offered in 144‑pin LQFP (PGE) and 144‑pin BGA (GGU) packages, with detailed pin‑assignment tables and electrical characteristics. The datasheet also covers absolute maximum ratings, recommended operating conditions, mechanical data, and revision history.
| ALU width | 40‑bit |
|---|---|
| On‑chip ROM | 4 K × 16‑bit |
| On‑chip RAM | 16 K × 16‑bit dual‑access |
| Maximum speed | 100 MIPS (10‑ns single‑cycle) |
| Maximum external program space | 1 M × 16‑bit |
| Package options | 144‑pin LQFP (PGE) and 144‑pin BGA (GGU) |
The DSP can execute a 10‑ns single‑cycle fixed‑point instruction, delivering up to 100 MIPS.
It is offered in a 144‑pin LQFP (PGE) package and a 144‑pin BGA (GGU) package.
The device includes 4 K × 16‑bit ROM and 16 K × 16‑bit dual‑access RAM on‑chip.
It integrates two multichannel buffered serial ports, an enhanced 8‑bit host‑port interface, two 16‑bit timers, a six‑channel DMA controller, a PLL clock generator, and JTAG boundary‑scan logic.