This document describes the S100B port failed connection issue of TSB41BA3/A and provides some workarounds
The document describes a $100B port failed‑connection issue on the TSB41BA3/A, where the port may not establish an active link after power‑up. The cause is identified as improper reset of the transmit clock circuitry, leading to an invalid frequency for S100B connections. Several software and hardware workarounds are provided, such as changing the device mode to S400B, using the CSEL bit in the page‑7 register, and performing hard resets.
A second issue, "Disappearing IDLE in a Beta system," can cause arbitration time‑outs and bus resets in systems with multiple cable hops. The recommended hardware workaround is to add a 1394A PHY to enforce legacy gap timing. The manual concludes with legal notices and warranty information from Texas Instruments.
| Loop_disable flag location | page‑0 port status register at Dh |
|---|---|
| CSEL bit location | page‑7 register |
The transmit clock circuitry is not properly reset at power‑up, allowing it to initialize into an invalid state that generates an incorrect frequency for S100B connections.
Add a 1394A PHY to the system to force legacy gap timing on the 1394 bus.