The 3D7105 family consists of monolithic 5‑tap fixed‑delay CMOS integrated circuits. Each device offers five uniformly spaced taps, TTL/CMOS compatibility, and both leading‑ and trailing‑edge accuracy. The part is offered in 14‑pin DIP and 16‑pin SOIC packages as drop‑in replacements for hybrid delay lines.
The datasheet lists electrical characteristics such as a delay range of 0.75‑80 ns, 5 % tolerance, temperature stability of +3 % (0 °C‑70 °C), and VDD stability of +1 % (4.75 V‑5.25 V). Detailed pin assignments, absolute maximum ratings, DC electrical parameters, and test conditions are provided for designers.
| Delay range | 0.75 ns to 80 ns |
|---|---|
| Delay tolerance | 5 % |
| Temperature stability | +3 % typical (0 °C‑70 °C) |
| VDD stability | +1 % typical (4.75 V‑5.25 V) |
| Minimum input pulse width | 30 % of total delay |
| Package options | 14‑pin DIP and 16‑pin SOIC |
| Supply voltage range | 4.75 V to 5.25 V |
| Static supply current | 30 mA |
| High level input voltage | 2.0 V |
| Low level input voltage | 0.8 V |
The 3D7105 provides a selectable delay from 0.75 ns up to 80 ns.
The device has five taps, each providing a buffered output at 10 % increments of the total delay.
It is offered in a 14‑pin DIP and a 16‑pin SOIC package.
Maximum operating frequencies range up to 41.7 MHz depending on the part number.