The 74LVC373A is a low voltage CMOS 8-bit D-type latch fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits
The 74LVC373A is a low‑voltage CMOS octal D‑type latch with high‑speed operation, power‑down protection and ESD immunity. It features symmetrical output impedance, balanced propagation delays and is compatible with the 74 series 373 pinout.
The document details absolute maximum ratings, recommended operating conditions, DC and AC electrical characteristics, dynamic switching parameters, capacitive data, waveform timing diagrams, and mechanical dimensions for both SO‑20 and TSSOP‑20 packages.
| Supply Voltage Range | 1.65 V to 3.6 V |
|---|---|
| High/Low Level Output Current (Vcc = 3.0‑3.6 V) | +24 mA |
| Input Capacitance | 4 pF |
The device operates with a supply voltage from 1.65 V to 3.6 V.
The input capacitance is 4 pF.
Each output can source or sink up to +24 mA when Vcc is between 3.0 V and 3.6 V.
The part is offered in SOP (SO‑20) and TSSOP (TSSOP‑20) packages.