This document describes the features and characteristics of a 64 Kbit (8K x 8) parallel EEPROM chip called M28C64. The chip has fast access time, software data protection, low power consumption, fast byte and page write capabilities, and enhanced write detection and monitoring. It also has JEDEC approved pin-out and software data protection. The chip supports 100,000 erase/write cycles and has a data retention of up to 40 years.
The M28C64 is a 64‑Kbit (8K × 8) parallel EEPROM offering fast access time, low power consumption, and software data protection. It operates from a single supply voltage (4.5 V‑5.5 V or 2.7 V‑3.6 V) and provides up to 100 k erase/write cycles with data retention of up to 40 years.
The device is available in several packages (PDIP28, SO28, PLCC32, TSOP28) and includes status bits and a Ready/Busy output for write‑cycle monitoring. Detailed electrical characteristics, timing diagrams, and protection mechanisms are described throughout the document.
| Memory size | 64 Kbit (8K × 8) |
|---|---|
| Supply voltage (5 V range) | 4.5 V to 5.5 V |
| Access time | 90 ns at VCC = 5 V |
| Write time (byte) | 1 ms at VCC = 4.5 V (M28C64‑A) |
| Endurance | ≥ 100 000 erase/write cycles |
| Data retention | 40 years (M28C64, M28C64‑xxW) |
| Operating temperature range | -40 °C to 125 °C |
The M28C64 operates from 4.5 V to 5.5 V for the 5 V version and from 2.7 V to 3.6 V for the 3 V version.
The device is rated for at least 100 000 erase/write cycles.
Software Data Protection is enabled by writing three specific data bytes to three distinct memory locations as defined in the protection algorithm.