This document introduces the dsPIC30F family of high-performance digital signal controllers from Microchip Technology Inc., which are used for motor control and power conversion. The document provides information on the high-performance features of the product and the functionality of the digital signal controllers.
The dsPIC30F family is a high‑performance 16‑bit digital signal controller designed for motor control and power conversion applications. It combines a modified Harvard architecture CPU with up to 30 MIPS, multiple on‑chip peripherals, and extensive flash and RAM resources.
The document provides detailed information on the core CPU, peripheral modules such as timers, PWM, ADC, CAN, and QEI, as well as pin‑out diagrams, package options, and ordering information for the various dsPIC30F devices.
| On‑chip Flash program space | Up to 144 KB |
|---|---|
| On‑chip data RAM | Up to 8 KB |
| Non‑volatile data EEPROM | Up to 4 KB |
| Instruction word width | 24‑bit |
| Maximum MIPS | 30 MIPS |
| PWM output channels | Up to 8 |
| ADC resolution | 10‑bit |
| ADC conversion rate | 500 Ksps |
| Interrupt sources | Up to 42 |
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The dsPIC30F offers up to eight PWM output channels.
The enhanced flash memory is rated for a minimum of 10,000 erase/write cycles in the industrial temperature range.
The 10‑bit ADC can operate at up to 500 Ksps conversion rate.