Microchip dsPIC30F5011/5013 Datasheet

About this manual

The dsPIC30F5011 and dsPIC30F5013 are high‑performance 16‑bit digital signal controllers featuring a modified Harvard RISC CPU, up to 30 MIPS operation, and a rich set of peripherals including timers, UART, CAN, and a 12‑bit ADC. They offer up to 66 KB on‑chip Flash, 4 KB RAM, and 1 KB EEPROM, with high‑current I/O pins capable of 25 mA sink/source.

The datasheet details the CPU architecture, memory organization, interrupt system, peripheral modules, pin diagrams for 64‑pin and 80‑pin TQFP packages, electrical characteristics, and packaging information, providing designers with all necessary data to integrate the devices into their applications.

What's inside

• Device Overview
• CPU Architecture
• Memory Organization
• Peripheral Modules (Timers, UART, CAN, ADC)
• Pin Diagrams
• Electrical Characteristics
• Packaging Information
• Instruction Set Summary

Specifications

Frequently asked questions

What is the maximum operating speed of the dsPIC30F5011/5013?

The devices can operate at up to 30 MIPS.

How much on‑chip Flash memory do the dsPIC30F5011/5013 provide?

Each device includes 66 KB of on‑chip Flash program memory.

How many ADC input channels are available?

The ADC supports up to 16 input channels.

What is the current capability of the I/O pins?

Each I/O pin can sink or source up to 25 mA.