Intersil ISL95810 Datasheet

The ISL95810 is a single digitally controlled potentiometer with low noise, low power I2C bus and 256 taps. It can be used as a three-terminal potentiometer or a two-terminal variable resistor in various applications including control, parameter adjustments, and signal processing.


Intersil ISL95810 Datasheet - cover page
Brand
Intersil
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
13
File format
PDF
File size
1 MB
Published
27 March, 2012
Updated
29 September, 2023
MD5 checksum
7884690F3849F87770CCD4869FEE3B39

About this manual

The ISL95810 is a single digitally controlled potentiometer (XDCP) integrated on a CMOS IC. It features 256 resistor taps, a volatile wiper register, non‑volatile initial‑value storage, and an I²C‑compatible serial interface for read/write operations.

The document includes pin descriptions, absolute maximum ratings, recommended operating conditions, analog and operating specifications, EEPROM endurance, serial interface timing, typical performance curves, and mechanical dimensions for MSOP and TDFN packages.

What's inside

  • Features
  • Ordering Information
  • Pin Descriptions
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • Analog Specifications
  • Operating Specifications
  • EEPROM Specifications
  • Serial Interface Specifications
  • Typical Performance Curves

Specifications

Resistor taps256
Wiper resistance (typical @ 3.3 V)70 Ω
Supply voltage range2.7 V to 5.5 V
Standby current5 µA max
Endurance (non‑volatile memory)200,000 data changes per bit per register
Data retention50 years @ ≤ +75 °C
Package types8‑Ld MSOP and 8‑Ld TDFN

Frequently asked questions

What is the supply voltage range for the ISL95810?

The device operates from 2.7 V up to 5.5 V.

How many resistor taps does the ISL95810 provide?

It provides 256 resistor taps.

What is the standby current of the ISL95810?

The standby current is specified as 5 µA maximum.

What is the endurance of the non‑volatile memory in the ISL95810?

The memory can endure 200,000 data changes per bit per register.

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