This document is a programming reference for the ADSP-TS201 TigerSHARC® processor, describing its features and characteristics.
This document is a programming reference for the ADSP-TS201 TigerSHARC® processor. It describes the processor architecture, compute blocks, instruction formats, and programming guidelines.
The reference includes sections on the ALU, CLU, multiplier, shifter, IALU, program sequencer, memory and bus organization, as well as a comprehensive index of registers and status flags.
| Number of cache sets | 128 |
|---|---|
| Number of cache ways | 16 |
| Number of words in cache | 128K |
It provides a programming reference for the ADSP-TS201 TigerSHARC processor.
The document describes compute block registers, ALU registers, CLU registers, multiplier registers, shifter registers, IALU registers, and universal registers.