This document provides a user's and hacker's guide to the SimpleScalar Architectural Research Tool Set. It covers a primer on computer architecture simulation, an overview and user's guide to the SimpleScalar tool set, the SimpleScalar Instruction Set Architecture, out-of-order issue simulator, hacking SimpleScalar, and a look ahead.
This guide, authored by Intel's MicroComputer Research Labs, introduces the SimpleScalar Architectural Research Tool Set (release 2.0) and explains its role as a computer‑architecture simulation environment. It outlines the purpose of architectural simulators, the taxonomy of simulation tools, and the design goals of the SimpleScalar suite.
The document details functional versus performance simulators, trace‑driven versus execution‑driven simulation, instruction scheduling versus cycle‑timer approaches, and the "Zen of Simulator Design" that balances performance, flexibility, and detail. It also lists related tools and provides a brief example of a fast functional simulator implementation.
| Tool set release | 2.0 |
|---|---|
| Supported host architecture | MIPS |
It is a tool that reproduces the behavior of a computing device.
Functional simulators implement the architecture, while performance simulators implement the microarchitecture.
Trace‑driven simulation reads a pre‑recorded instruction trace, whereas execution‑driven simulation runs the program and generates a trace on‑the‑fly.
It optimizes performance and flexibility.