Industrial

This file provides the pin definitions for the EPF6016A device, including 100-Pin TQFP, 100-Pin FineLine BGA, 144-Pin TQFP, 208-Pin PQFP, and 256-Pin FineLine BGA packages

EPF10K100B Device Pin-Outs

Pin-Outs for EPF10K50S device, including 144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 256-Pin FineLine BGA, 356-Pin BGA and 484-Pin FineLine BGA

This is a pinout for EP1K30 device. It lists all the pin functions and corresponding pin numbers.

EP1K10 device pin-out

Altera Corporation has released preliminary release notes for the SerialLite II MegaCore function. This function contains the following information: system requirements, new features and enhancements, Adobe Reader version 5.0 or higher for viewing PDF documentation, obtaining and installing the SerialLite II MegaCore function, contacting Altera, and revision history.

This document is a preliminary release notes for the HyperTansport MegaCore function version 1.4.0 released by Altera company. It contains the system requirements, new features, enhancements, fixes, and how to obtain and install the function.

This chapter describes the hardware features that support high-speed memory interfacing for each double data rate (DDR) memory standard in HardCopy® III devices. HardCopy III devices feature delay-locked loops (DLLs), phase-locked loops (PLLs), dynamic on-chip termination (OCT), read-and-write leveling, and deskew circuitry. This chapter contains the following sections:...

This document describes the I/O features of Altera's Cyclone V devices, including support for different types of I/O standards and requirements.

This document introduces how to use Altera's Stratix II GX FPGA for thermal design

This document is about the pin information of EPM240 device, including IO/GCLK0, IO/GCLK1, IO/GCLK2, IO/GCLK3, IO/DEV_OE, IO/DEV_CLRn, TDI, TMS, TCK, TDO, GNDINT, GNDIO, VCCINT, VCCIO1, VCCIO2

This is a document about Altera Cyclone III device family pin connection guidelines

This document is an introduction to PLL design and usage in Altera Cyclone FPGAs

Describes the I/O standards supported by the Altera Stratix and Stratix GX devices