MOTOROLA Manuals

The MC10E/100E156 is a 3-BIT 4:1 MUX-LATCH circuit with differential outputs, asynchronous master reset, dual latch-enables, extended 100E VEE range of -4.2V to -5.46V, and 75kΩ input pulldown resistors.

This product is the MC10E/100E155 chip data sheet, which introduces the function characteristics, pin definition, logic diagram and other information of the chip.

This document is MC10E/100E155 datasheet, introduces the function and characteristics of the chip, including pin definition, logic diagram, truth table, characteristic parameters, etc.

The MC10E/100E151 is a 6-bit D register produced by Motorola. It has a minimum toggle frequency of 1100MHz, differential outputs, asynchronous master reset, dual clocks, an extended 100E VEE range from -4.2V to -5.46V, and 75kΩ input pulldown resistors.

The MC10E/100E151 is a 6-BIT D REGISTER produced by Motorola Corporation. It has 1100MHz Min. Toggle Frequency, Differential Outputs, Asynchronous Master Reset, Dual Clocks, Extended 100E VEE Range of – 4.2V to – 5.46V, 75kΩ Input Pulldown Resistors and other features.

The MC10E/100E150 is a 6-bit D latch with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.

MC10E/100E150 is a 6-bit D latch with differential outputs produced by Motorola. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low.

The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0 – D8 accepting parallel input data.

The MC10E/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0 – D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

MC10E/100E141 is an 8-bit full-function shift register. It performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0-D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.

MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry output and accepts a look-ahead-carry input. These two features allow for the cacading of multiple E136’s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter.

MC10E/100E131 is a quad master-slave D-type flip-flop with differential outputs, released by Motorola in 1996. The device can be clocked separately by keeping the common clock (CC) low and using the clock enable (CE) inputs for clocking. Common clocking is achieved by keeping the CE inputs low and using CC to clock all four flip-flops. In this case, the CE inputs perform the function of controlling the common clock to each flip-flop. Individual asynchronous resets are provided (R). Asynchronous set controls (S) are ganged together in pairs, with the pairing chosen to reflect physical chip symmetry. Data enters the master when both CC and CE are LOW, and transfers to the slave when either CC or CE (or both) go HIGH.