MOTOROLA Manuals

The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family, featuring high-performance CPU system, peripheral pin multiplexing, flash and code compression options.

This is a transistor with two resistors integrated, which can simplify circuit design, reduce board space and reduce the number of components.

Introduced the functional characteristics of the MC74F195 4-Bit Parallel Access Shift Register. The device is useful in a wide variety of shifting, counting, and storage applications. It performs serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at very high speeds.

MCM67J618B is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium microprocessors.

This document is about MC74HC367A technical data sheet. The chip has a 15 LSTTL load drive capability, outputs directly interface to CMOS, NMOS, TTL, operating voltage range is 2 to 6V, input current is 1µA, complies with JEDEC standard 7A requirements, and chip complexity is 92 FETs or 23 equivalent gates.

This manual introduces the setup and use of WR850GP/WR850G wireless broadband routers.

The MC10103 is a quad 2-input OR gate that provides one gate with OR/NOR outputs. It has low power consumption and fast response time.

MC54/74HC138A is the upgraded version of MC54/74HC138, which supports LSTTL output. This chip can decode three-bit address into eight outputs, and supports three selection functions: decoding, cascading and selection.

The MC74LVQ138 is a high performance, 1–of–8 decoder/ demultiplexer operating from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. The MC74LVQ138 is suitable for memory address decoding and other TTL level bus oriented applications.

The MCM64PC32 (256K) and MCM64PC64 (512K) are designed to provide a burstable, high performance, L2 cache for the Pentium microprocessor in conjunction with Intel’s Triton II chip set. The MCM64PC32 is configured as 32K x 64 bits and the MCM64PC64 is configured as 64K x 64 bits. Both are packaged in a 160 pin card edge memory module. Each module uses Motorola’s 3.3 V 32K x 32 BurstRAMs and one Motorola 3.3 V 32K x 8 FSRAM for the tag RAM. Bursts can be initiated with either address status processor (ADSP) or cache address status (CADS). Subsequent burst addresses are generated internal to the BurstRAM by the cache burst advance (CADV) input pin. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLK0) input. Eight write enables are provided for byte write control. PD0-PD3 map into the Triton II chip set for auto-configuration of the cache control. Pentium-Style Burst Counter on Chip. Pipelined Data Out. 160 Pin Card Edge Module. Address Pipeline Supported by ADSP Disabled with Ex. All Cache Data and Tag I/Os are TTL Compatible. Three State Outputs. Byte Write Capability. Fast Module Clock Rate: 66 MHz. Fast SRAM Access Times: 15 ns for Tag RAM, 8 ns for Data RAMs. One-Cycle Deselect Data RAMs. Decoupling Capacitors for Each Fast Static RAM. High Quality Multi-Layer FR4 PWB with Separate Power and Ground.

This integrated circuit is intended for GSM class IV handsets. The device is specified for 2.5 Watts output power and 43% minimum power added efficiency under GSM signal conditions at 3.6 Volt supply voltage. To achieve this superior performance, Motorola's planar GaAs MESFET process is employed. The device is packaged in the PFP-16 Power Flat Pack package which gives excellent thermal performance through a solderable backside contact.

The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP) that combines an efficient 16-bit digital signal processing core, program and data memories, multiple peripherals, and system support circuitry on a single semiconductor chip. Unique features of the DSP56156 include a built-in sigma-delta (²ý) codec and phase-locked loop (PLL), making it a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations.