MOTOROLA Manuals

This data sheet provides information about the MC10E/100E171 3-Bit 4:1 MULTIPLEXER, including pin names, functions, and voltage ranges

The MC10E/100E167 contains six 2:1 multiplexers followed by D flip-flops with single-ended outputs. Input data are selected by the Select control, SEL. The selected data are transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2 (or both). A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.

The MC10E/100E167 is a 6-bit 2:1 multiplexer with single-ended outputs. Input data is selected by the Select control (SEL) and transferred to the flip-flop outputs by a positive edge on CLK1 or CLK2. A HIGH on the Master Reset (MR) pin asynchronously forces all Q outputs LOW.

The MC10E/100E166 is a 9-bit magnitude comparator that compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other.

The MC10E/100E166 is a 9-bit magnitude comparator that compares the binary value of two 9-bit words and indicates whether one word is greater than, or equal to, the other.

The MC10E1651 is functionally and pin-for-pin compatible with the MC1651 in the MECL III family, but is fabricated using Motorola’s advanced MOSAIC III process. The MC10E1651 incorporates a fixed level of input hysteresis as well as output compatibility with 10KH logic devices. In addition, a latch is available allowing a sample and hold function to be performed. The device is available in both a 16-pin DIP and a 20-pin surface mount package. The latch enable (LENa and LENb) input pins operate from standard ECL 10KH logic levels. When the latch enable is at a logic high level the MC10E1651 acts as a comparator, hence Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state providing the latch enable setup and hold time constraints are met.

The MC10E/100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0, 1, 2, 3 ) control which one of the sixteen data inputs (A0 – A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 50ps.

This data sheet provides MC10E/100E164 data, including product features, pin definitions, package dimensions, electrical characteristics, etc.

The MC10E/100E163 are two 8:1 multiplexers with differential outputs and common select inputs, produced by Motorola. The select inputs (SEL0, 1, 2) control which one of the eight data inputs (A0-A7, B0-B7) is propagated to the output.

The MC10E/100E160 is a 12-bit parity generator/checker. When the number of input highs is odd, the Q output is high. A high on the Enable input (EN) forces the Q output low. The E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A high on the reset pin (R) overrides to force the Y output low.

The MC10E/100E158 is a product that contains five 2:1 multiplexers with differential outputs. The output data are controlled by the Select input (SEL). This product features fast delay characteristics and a wide operating voltage range.

MC10E/100E156 is 3-BIT 4:1 MUX-LATCH, includes three 4:1 multiplexers, followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.